The present invention relates to a semiconductor device and a method for fabricating the semiconductor device, more specifically a semiconductor device which can realize further micronization and a method for fabricating the semiconductor device.
SRAM (Static Random Access Memory) is a semiconductor memory device the memory cell of which is a flip-flop circuit and which is operative at high speed. A CMOS-type SRAM, which comprises the load transistor in the form of a p-channel transistor and the driver transistor in the form of an n-channel transistor, is prevalently used in fields requiring very little source current in stand-by and small consumption electric power.
In the process of fabricating the CMOS-type SRAM, 6 transistors forming a basic unit of the memory cell are formed on a semiconductor substrate, then an inter-layer insulation film for covering the transistors are formed, and an interconnection interconnecting the electrodes of the respective transistors is formed on the inter-layer insulation film.
The proposed SRAM will be explained with reference to FIGS. 33 and 34. FIG. 33 is a sectional view of the proposed SRAM. FIG. 34 is a plan view of the proposed SRAM, which show the pattern thereof.
P-type wells 116p and n-type wells 116n are formed on a semiconductor substrate 114. On the semiconductor substrate 114 with the p-type wells 116p and the n-type wells 116n formed on, device isolation regions 120 for defining device regions 118a–118d are formed. Gate interconnections 124a–124d are formed on the semiconductor substrate 114 with a gate insulation film 122 formed on. A sidewall insulation film 126 is formed on the side walls of the gate interconnections 124a–124d. 
The gate interconnection 124a is formed, crossing the device regions 118a, 118b. The gate interconnection 124a includes the gate electrode of a load transistor L1 and the gate electrode of a driver transistor D1 and commonly connects the gate electrode of the load transistor L1 and the gate electrode of the driver transistor D1. In the device region 118a on both side of the gate interconnection 124a, a source/drain diffused layer 130, 131 is formed. The gate electrode 124a and the source/drain diffused layer 130, 131 form the load transistor L1. In the device region 118b on both side of the gate interconnection 124a, a source/drain diffused layer 132, 133 is formed. The gate electrode 124a and the source/drain diffused layer 132, 133 form the driver transistor D1.
The gate interconnection 124b is formed, crossing the device regions 118c, 118d. The gate interconnection 124b includes the gate electrode of a load transistor L2 and the gate electrode of a driver transistor D2 and commonly connects the gate electrode of the load transistor L2 and the gate electrode of the driver transistor D2. In the device region 118c on both side of the gate interconnection 124b, a source/drain diffused layer 128, 129 is formed. The gate electrode 124b and the source/drain diffused layer 128, 129 form the load transistor L2. In the device region 118d on both side of the gate interconnection 124b, a source/drain diffused layer 134, 135 is formed. The gate electrode 124 band the source/drain diffused layer 134, 135 form the driver transistor D2.
The gate interconnection 124c is formed, crossing the device region 118b. The gate interconnection 124c includes the gate electrode of a transfer transistor T1 and commonly connects the gate electrodes of the transfer transistors T1 formed in the memory cells adjacent to each other. In the device region 118b on both sides of the gate interconnection 124c, a source/drain diffused layer 132, 136 are formed. The gate electrode 124c and the source/drain diffused layer 132, 136 form the transfer transistor T1.
The gate interconnection 124d is formed, crossing the device region 118d. The gate interconnection 124d includes the gate electrode of a transfer transistor T2 and commonly connects the gate electrode of the transfer transistor T2 formed in the memory cells adjacent to each other. In the device region 118d on both sides of the gate interconnection 124d, a source/drain diffused layer 134, 137 is formed. The gate electrode 124d and the source/drain diffused layer 134, 137 form the transfer transistor T2.
A stopper film 138 is formed on the semiconductor substrate 114 with these transistors L1, L2, D1, D2, T1, T2. An inter-layer insulation film 140 is formed on the semiconductor substrate with the stopper film 138.
Contact holes 142 are formed in the inter-layer insulation film 140 down to the gate interconnections 124a–124d and the source/drain diffused layer 128–137. In the contact holes 142, a contact layer 148, 148a, 148b formed of a barrier film 144 and a tungsten film 146 is buried. The gate interconnection 124a and the source/drain diffused layer 128 are interconnected to each other by the contact layer 148a. The gate interconnection 124b and the source/drain diffused layer 130 are interconnected to each other by the contact layer 148b. 
A stopper film 174 is formed on the inter-layer insulation film 140 with the contact layer 148, 148a, 148b buried in. An inter-layer insulation film 176 is formed on the stopper film 174. Groove-shaped openings 178 for exposing the contact layer 148 are formed in the inter-layer insulation film 176. In the groove-shaped openings 178, interconnections 150 formed of a barrier film 180 and a Cu film 181 is buried.
Thus, the proposed SRAM is constituted.
Following references disclose the background art of the present invention.
[Patent Reference 1]
Specification of Japanese Patent Application Unexamined Publication No. 2003-45961
[Patent Reference 2]
Specification of Japanese Patent Application Unexamined Publication No. 2001-93974
[Patent Reference 3]
Specification of Japanese Patent Application Unexamined Publication No. Hei 9-162354
[Patent Reference 4]
Specification of Japanese Patent Application Unexamined Publication No. Hei 9-55440.
[Patent Reference 5]
Specification of Japanese Patent Application Unexamined Publication No. 2003-131400
Recently, for lower costs and larger capacities, the memory cell is required to be further micronized. To micronize the memory cell, it is very important to form micronized contact holes without failure. As techniques which can form micronized contact holes are proposed the technique using modified light, such as zonal light or others, the technique using a halftone phase shift mask, the technique forming an auxiliary pattern (assist pattern or scattering bar), and other techniques. However, these techniques have found it very difficult to form about 90 nm×90 nm micronized contact holes without failure. Accordingly, further micronization leads to reliability decrease and lower fabrication yields.